1. Field of the Invention
The present invention relates to a voltage-controlled oscillator which can change a frequency of a signal to be generated, based on a control voltage, a semiconductor integrated circuit and a phase-locked loop (PLL) circuit using the voltage-controlled oscillator, and an intermediate-frequency processing circuit using the phase-locked loop circuit.
2. Description of the Related Art
Recently, mobile communication devices in accordance with standards such as PDS (Personal Digital Cellular), PHS (Personal Handy Phone) and so forth have rapidly become popular. This is because semiconductor chips incorporated into such devices have been miniaturized and, thereby, the devices have been miniaturized and the weights thereof have been reduced. Further, miniaturization of semiconductor chips incorporated into mobile communication devices is demanded, and, also, it is demanded that such semiconductor chips consume less energy. Forming circuits by CMOS (Complementary Metal Oxide Semiconductor) and, thus, integrating the circuits into one chip as much as possible is effective to obtain a miniaturized less-energy-consuming semiconductor chip. Thereby, it is possible to reduce the cost of semiconductor components.
Noise transmission between circuits is a problem in forming circuits of a communication device in one chip. An intermediate-frequency (IF) processing circuit portion of a communication device includes a phase-locked loop (PLL) circuit which generates a local frequency on the order of 200 through 300 MHz, a voltage-controlled oscillator (VCO), a mixer which adjusts a carrier frequency of transmission and reception signals, an IF amplifier which amplifies a signal from the mixer, a modulator which modulates transmission and reception signals, and a filter. In the intermediate-frequency processing circuit portion, the VCO, mixer, IF amplifier, and modulator are analog circuits while the PLL circuit is a digital circuit. Therefore, an analog and digital mixed chip is formed. In the analog and digital mixed chip, it is necessary to physically and electrically separate a circuit block of a analog portion and a circuit block of a digital portion.
In Japanese Laid-Open Patent Application No. 6-120424, an art is disclosed in which leads and pads for supplying power to a digital output circuit are provided separately from leads and pads for supplying power to the other circuits, and, thereby, noise generated at a time of switching in the digital output circuit is prevented from adversely affecting analog circuits.
A VCO used in a PLL circuit for a communication device is demanded to have low jitter and high C/N (Carrier/Noise) characteristics. It is necessary to dispose the VCO separately from the other analog circuits in order to prevent the VCO from being affected by noise. A VCO in the prior art uses an LC oscillator or an RC oscillator in many cases. In such cases, at least L and C portions are externally connected. Thereby, noise transmission between the VCO and other circuits has not been a problem. However, when a whole VCO is formed by CMOS in one chip, it is necessary to form the VCO so as not to receive noise or to dispose the VCO so as not to receive noise.
In Japanese Laid-Open Patent Application No. 6-204297, an art is disclosed in which a terminal of the ground of an oscillating circuit and a terminal of the ground of another high-frequency circuit are separated and bonded in a package, thereby, isolation is performed, and, thus, the oscillating circuit and the other high-frequency circuit are formed in one chip.
The above-described two prior arts are methods for preventing noise generated by a circuit from being transmitted to another circuit. However, these methods are different from a fundamental method for preventing generation of noise itself.
In Japanese Laid-Open Patent Application No. 7-7420, an art is disclosed in which a current-constant logic is used in a phase comparing circuit of a PLL circuit, thereby, noise being prevented from being transmitted to another circuit via a power source, as a result of a passing-through current of a logic circuit being caused to be constant. This art is an example of preventing generation of noise by a circuit itself. However, this art does not include prevention of noise generation by a VCO which can be a large noise source.
A VCO in a PLL circuit has characteristics thereof degraded by a power-source voltage variation and/or noise from another circuit. Further, the VCO in the PLL circuit is a circuit which has the highest oscillation frequency and the largest oscillation amplitude in a chip, and, thereby, is a noise generation source. In particular, in the case of a VCO formed of CMOS, a passing-through current varies at a frequency same as the oscillation frequency. This variation in the passing-through current causes a variation in the power-source voltage, and, thus, power-source noise occurs. Further, due to parasitic capacitance coupling or radiation between adjacent signal lines, an oscillation signal on one signal line is transmitted to another signal line as noise. Such noise transmission may not be sufficiently eliminated as a result of providing a separate power source for the VCO and/or physically and electrically separating a VCO block. Therefore, it is important to reduce noise generated by the VCO.
In Japanese Laid-Open Patent Application No. 8-162911, an art is disclosed in which charging and discharging of a capacitor which is included in an oscillation circuit is performed by a constant current, and, thereby, the value of the constant current of the VCO which is oscillating is changed so that the oscillation frequency is controlled. In this art, the oscillation amplitude can be set to an arbitrary value. However, an operational amplifier is used as a comparator. Thereby, a circuit scale is large, and, also, a capacitor having a relatively large capacitance is needed. Therefore, the arrangement of this art is not suitable to be formed by CMOS in one chip.
In Japanese Laid-Open Patent Application No. 8-18408, a VCO is disclosed in which an odd number of inverter circuits of CMOS circuits are connected to form a ring (ring oscillator). In such a VCO, a comparator is not needed. Further, in Japanese Laid-Open Patent Application No. 8-18408, an arrangement is also disclosed in which a constant-current element is connected between adjacent inverter circuits in series which are included in a ring oscillator. Thereby, it is possible to provide high-frequency oscillation using a low-voltage power source, and, also, it is possible to reduce power consumption even when a high-voltage power source is used.
In `A 320 MHz CMOS Triple 8 bit DAC with On-Chip PLL and Hardware Cursor`, David Reynolds, IEEE JOURNAL OF SOLID-STATE CIRCUIT, Vol. 29, No. 12, December, 1994, use of a ring oscillator is disclosed, which ring oscillator includes differential-amplifier-type inverters through each of which a steady current flows. Thereby, a VCO which performs oscillation in a wide frequency range can be obtained. By this arrangement, it is possible to reduce a signal amplitude of the VCO and reduce noise generation.
Each of power source voltages of almost all of mobile communication devices which have been used currently is 3.3 V. As mentioned above, a semiconductor chip for a mobile communication device is demanded to consume less power so as to elongate a life of a battery. Reducing a power-source voltage is effective for reducing power consumption. However, as a result of reduction of the power-source voltage, a speed of operation of a circuit decreases. As a result, it may be difficult to form a PLL circuit by CMOS, which PLL circuit generates a local frequency (on the order of 230 MHz) of an IF circuit portion. In order to obtain a distortion-free oscillation waveform of 230 MHz from a PLL circuit, a VCO needs to oscillate at a frequency double the frequency of 230 MHz.
In Japanese Laid-Open Patent Application 8-18408, a VCO is disclosed which uses voltage-controlled inverter circuits, each inverter circuit including two p-channel MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) and two n-channel MOSFETs connected in series. In this VCO, it is difficult to obtain 460 MHz (actually, 550 MHz, as a result of an increase by approximately 20% in consideration of a process design margin) in a stable condition using the power source of 1.5 V. Further, in this method, because the range of the oscillation voltage (double the oscillation amplitude) is the range from 0 through VCC, as shown in FIG. 6, a large amount of noise is generated, and, therefore, such a VCO is not suitable as a VCO for a PLL circuit for communication.
A VCO in which an odd number of CMOS inverter circuits are connected to form a ring is shown in FIG. 1. In the VCO shown in FIG. 1, a gate capacitance, a wiring capacitance and a drain junction capacitance are collected and replaced by an equivalent additive capacitance C.sub.L. The delay time of the signal of each inverter circuit is short when the additive capacitance C.sub.L is small and charging and discharging currents are large. Thereby, the oscillation frequency is high. FIG. 2 is obtained as a result of lines for supplying a first control signal (Pcon) and a second control signal (Ncon) being added to the arrangement shown in FIG. 1.
An arrangement in which an inverter circuit shown in FIG. 3 is used is disclosed in Japanese Laid-Open Patent Application No. 8-18408. In this arrangement, the oscillation frequency varies by control signals (Pcon, Ncon) which are supplied by a VCO bias generating circuit (not shown in the figure). When IN is at a low level, by a current (Ip) supplied from VCC through two p-channel MOSFETs (P1, P2), as shown in FIG. 4A, the additive capacitance C.sub.L is charged. When IN is at a high level, by a current (In) passing through two n-channel MOSFETs (N1, N2), as shown in FIG. 4B, the additive capacitance C.sub.L is discharged. In this method, the n-channel MOSFET (N1) and p-channel MOSFET (P1) alternately perform turning on and turning off repetitively. As a result, the range of the oscillation voltage extends from 0 through VCC. That is, it is necessary to fully charge and discharge the additive capacitance C.sub.L so as to change the voltage of the additive capacitance C.sub.L between 0 and VCC. As a result, it is impossible to obtain a high oscillation frequency. In FIGS. 4A and 4B, the ON resistances of the FETs N1 and N2 are indicated by an equivalent variable resistance Rn12, and the ON resistances of the FETs P1 and P2 are indicated by an equivalent variable resistance Rp12.
In `A 320 MHz CMOS Triple 8 bit DAC with On-Chip PLL and Hardware Cursor`, David Reynolds, IEEE JOURNAL OF SOLID-STATE CIRCUIT, Vol. 29, No. 12, December, 1994, a method is disclosed in which, as a result of the VCO in which the differential-amplifier-type inverters are connected to form a ring being used, the amplitude of the oscillation signal decreases when the oscillation frequency increases. However, the oscillation waveform is present on the side of VCC with respect to VCC/2. A level converting circuit is needed for shifting the oscillation waveform so that the central value of the oscillation waveform is VCC/2. Thus, the circuit becomes complicated. Further, when the level converting circuit is provided, the oscillation circuit needs to have a high driving capability. Further, when symmetry of the complementary transistors of each inverter circuit is not complete, this may cause jitter.